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ICM-42688P — 6-Axis Inertial Sensor Module

Manufacturer: Shenzhen HuaXuanYang (HXY) Electronics CO., LTD Website: www.hxymos.com


Description

The ICM-42688P is a highly integrated, low-power inertial measurement unit (IMU) with a built-in high-performance 3-axis accelerometer and 3-axis gyroscope measurement unit. The accelerometer full-scale range is +/-2g/+/-4g/+/-8g/+/-16g. The gyroscope angular rate full-scale range is +/-125dps/+/-250dps/+/-500dps/+/-1000dps/+/-2000dps. Users can flexibly measure external acceleration and angular velocity, with accelerometer output data rate from 0.78 Hz to 1.6 kHz selectable, and gyroscope output data rate from 25 Hz to 3.2 kHz selectable.

The chip communicates with the MCU via I2C/SPI interface. Accelerometer and gyroscope measurement data can be obtained by interrupt or polling. INT1 and INT2 interrupt pins provide various internal auto-detection interrupt signals for diverse motion detection scenarios, enabling reliable motion detection, attitude estimation, and gesture recognition at extremely low system power. Interrupt sources include 6D/4D orientation detection, free-fall detection, sleep and wake detection, single-tap and multi-tap detection, step counting, pedometer, and OIS function interrupts, as well as temperature detection interrupts.

The chip has a built-in high-precision calibration reference and an internal LDO circuit. At different supply voltages, zero drift remains more stable, correcting sensor gain errors and gain mismatch for precise angle-to-angle conversion testing. The chip has a built-in self-test function that allows customer system testing to detect system functionality, eliminating complex angle-to-angle conversion testing.

The ICM-42688P is applicable to smartphones, drones, game controllers, various IoT, and smart hardware systems. It supports mainstream operating systems for micro-step and motion capture screen functionality, and provides drones, game controllers, VR, and AR algorithm support.

Key Features

  • Analog supply voltage range: 1.71~3.6V
  • Low-power mode total combined supply current: 399uA
  • High-performance mode total combined supply current: 927uA
  • Accelerometer and gyroscope 16-bit data output
  • I2C/SPI digital output interface
  • Built-in temperature sensor
  • 6D/4D orientation detection, tilt detection/angle detection, static and motion detection
  • Sleep and wake detection, free-fall detection, single-tap and multi-tap detection
  • SensorTime function
  • OIS function (ODR=6.4kHz)
  • Programmable interrupt generation circuit
  • Built-in programmable step counter detection, built-in programmable wrist tilt recognition, built-in self-test function
  • Built-in FIFO
  • 10,000g high shock resistance
  • EU-compliant lead-free package, environmentally friendly

Applications

  • AR/VR devices
  • Smartphones and tablets
  • Smart wearable devices
  • Head-mounted device accessories
  • Attitude detection equipment
  • Image rotation scene switching
  • Strike detection scene activation
  • Motion detection devices
  • 9D orientation detection scenarios
  • Gesture recognition scenarios
  • Vibration detection and compensation scenarios
  • Indoor navigation / pedestrian path tracking / positioning scenarios
  • 3D scanning / indoor mapping / SLAM scenarios
  • Virtual reality games
  • Mouse / game controllers
  • IoT application scenarios
  • Optical image stabilization for cameras
  • Toy drones

Product Classification

Product NamePackage TypeMaterialPackaging
ICM-42688PLGA-14-2.5x3x1.00Lead-freeTape and reel

Package


Internal Block Diagram

Block Diagram

The internal architecture includes:

  • MEMS gyroscope drive (CV, Demod, LPF, VCO, MUX/VGA) with quadrature compensation
  • MEMS accelerometer sensing (CA channels for X/Y/Z with Demod and ADC)
  • Gyroscope sensing (CV + ADC for X/Y/Z axes)
  • Digital LPF, Composite Filter
  • Temperature compensation and sensor
  • I2C/SPI interface (CS, SCL/SCK, SDA/SDI, SDO)
  • Clock generator, Phase generator
  • FIFO, Power Management (PM), Reference (REF)
  • Control Logic and Interrupt Generation (INT1, INT2)
  • BIAS generator, Charge Pump (CP)

Absolute Maximum Ratings

ParameterSymbolTest ConditionsMinMaxUnit
Supply VoltageVDD/VDDIONo circuit damage-0.33.6V
Any Control PinV_inNo circuit damage (CS/SDO/SCL/SDA/INT1/INT2)-0.3VDDIO+0.3V
Operating TemperatureT_OPRNo circuit damage-40+85degC
Storage TemperatureT_STGNo circuit damage-55+150degC
ESDHBM4kV
ESDCDM1.5kV

Pin Description

Package: LGA14-2.5x3x1.00mm3

Package Dimensions

Acceleration Direction

X, Y, Z axes as marked on package (pin 1 indicator dot at corner).

Gyroscope Direction (top view)

+Omega_X, +Omega_Y, +Omega_Z rotation axes as marked.

Pin Table

Pin #NameI/O TypeDescription
1SDO/SA0I/OSPI 4-wire interface data output SDO; I2C device address LSB SA0
2ASDxI/OOIS interface
3ASCxOOIS interface
4INT1I/OInterrupt 1
5VDDIOSDigital power supply
6GNDIOGNDGround
7GNDGNDGround
8VDDSAnalog power supply
9INT2I/OInterrupt 2
10OCSBI/OOIS interface
11OSDOI/OOIS interface
12CSBII2C and SPI select: 1 = I2C; 0 = SPI
13SCXII2C clock SCL; SPI clock SPC
14SDXI/OI2C data SDA; SPI data input SDI; 3-wire SPI data output SDO

Mechanical Parameters — Accelerometer (VDD=1.8V, T_A=25degC)

ParameterSymbolTest ConditionsMinTypicalMaxUnit
Accelerometer Full-Scale RangeAF_S0A_FS=0+/-2.0g
AF_S1A_FS=1+/-4.0g
AF_S2A_FS=2+/-8.0g
AF_S3A_FS=3+/-16.0g
Accelerometer Sensitivity (16-bit)ASo0A_FS=00.061mg/digit
ASo1A_FS=10.122mg/digit
ASo2A_FS=20.244mg/digit
ASo3A_FS=30.488mg/digit
Accelerometer Sensitivity ErrorAS_ERRA_FS=0+/-2%
Accelerometer Temperature Sensitivity CoefficientAT_CSOA_FS=0, -40degC~85degC vs T=25degC diff+/-0.01%/degC
Accelerometer Zero DriftATY_OffA_FS=0, socket pressure test+/-80mg
Accelerometer Zero Drift Temperature CoefficientATC_offMax deviation from 25degC+/-1mg/degC
Accelerometer Non-LinearityANLBest fit line, A_FS=20.5%FS
Accelerometer Power Supply Rejection RatioAPSRRT_A=25degC+/-0.2mg/V
Accelerometer Cross-Axis InterferenceAS_XA_FS=0, interference between any two of three axes2%
Accelerometer Output Noise 1ARMS1A_FS=0, A_ODR=100Hz, High-perf mode, OSR4_AVG10.6mg
Accelerometer Output Noise 2ARMS2A_FS=0, A_ODR=100Hz, Low-power mode, OSR4_AVG14.5mg
Accelerometer Output Data RateAODR_A,HHigh-performance mode12.51600Hz
AODR_A,LPMLow-power mode0.78800Hz
Accelerometer System BandwidthABWODR/3ODR/2Hz
Accelerometer Self-Test OutputAV_st1A_FS=3, X-axis, high-freq oscillation, absolute value of positive/negative amplitude difference6g
AV_st2A_FS=3, Y-axis, same6g
AV_st3A_FS=3, Z-axis, same8g
Accelerometer Operating TemperatureAT_OPR-40+85degC

Note: Circuit is factory calibrated at 1.8V. Actual operating voltage is 1.71V-3.6V.


Mechanical Parameters — Gyroscope (VDD=1.8V, T_A=25degC)

ParameterSymbolTest ConditionsMinTypicalMaxUnit
Gyroscope Full-Scale RangeGF_S0G_FS=+/-125dps+/-125dps
GF_S1G_FS=+/-250dps+/-250dps
GF_S2G_FS=+/-500dps+/-500dps
GF_S3G_FS=+/-1000dps+/-1000dps
GF_S4G_FS=+/-2000dps+/-2000dps
Gyroscope Sensitivity (16-bit)GSo0G_FS=+/-125dps3.8125mdps/LSB
GSo1G_FS=+/-250dps7.625mdps/LSB
GSo2G_FS=+/-500dps15.25mdps/LSB
GSo3G_FS=+/-1000dps30.5mdps/LSB
GSo4G_FS=+/-2000dps61mdps/LSB
Gyroscope Temperature Sensitivity CoefficientGT_CSOG_FS=+/-2000dps, -40deg~85deg vs T=25deg diff+/-0.05%/degC
Gyroscope Sensitivity ErrorGS_ERRG_FS=+/-2000dps, calibrated+/-1.5%
Gyroscope Zero DriftGTY_OffG_FS=+/-2000dps, socket pressure test+/-0.2dps
Gyroscope Zero Drift Temperature CoefficientGTC_offG_FS=+/-2000dps, max deviation from 25degC+/-0.05dps/degC
Gyroscope Non-LinearityGNLBest fit line, G_FS=+/-2000dps0.1%FS
Gyroscope Cross-Axis InterferenceGS_XG_FS=+/-2000dps2%
Gyroscope Noise DensityGNG_FS=+/-2000dps, high-perf mode, GYR_BWP[1:0]=006mdps/sqrt(Hz)
Gyroscope Output Data RateGODR_G,HNHigh-perf / Normal mode253200Hz
GODR_G,LPMLow-power mode25800Hz
Operating TemperatureT_OPR-40+85degC

Note: Circuit is factory calibrated at 1.8V. Actual operating voltage is 1.71V-3.6V.


Electrical Parameters (VDD=1.8V, T_A=25degC)

ParameterSymbolTest ConditionsMinTypicalMaxUnit
Supply VoltageV_DD1.711.83.6V
IO Supply VoltageV_DDIO1.623.6V
Power ConsumptionI_DDA+G High-perf mode, VDD=1.8V, T_A=25degC, ODR_1.6kHz927uA
A+G Normal mode, VDD=1.8V, T_A=25degC, ODR_1.6kHz670uA
A+G Low-power mode, VDD=1.8V, T_A=25degC, ODR_25Hz399uA
A-only High-perf mode, VDD=1.8V, T_A=25degC, ODR_1.6kHz299uA
A-only Low-power mode, VDD=1.8V, T_A=25degC, ODR_25Hz13.3uA
A+G Off (shutdown), VDD=1.8V, T_A=25degC6uA
Power-Down CurrentI_DDPdn6uA
Digital High-Level Input VoltageV_IH0.8*V_DDIOV
Digital Low-Level Input VoltageV_IL0.2*V_DDIOV
High-Level Output VoltageV_OH0.9*V_DDIOV
Low-Level Output VoltageV_OL0.1*V_DDIOV
Startup TimeT_onODR=100Hz50ms
Operating TemperatureT_opr-40+85degC

I2C Control Interface Parameters (=1.8V, TA=25degC)

ParameterSymbolI2C Standard ModeI2C Fast ModeUnit
MINMAXMINMAX
SCL Clock Frequencyf_(SCL)01000400kHz
SCL Clock Low Timet_w(SCLL)4.71.3us
SCL Clock High Timet_w(SCLH)4.00.6us
SDA Setup Timet_su(SDA)250100ns
SDA Data Hold Timet_h(SDA)0.013.450.010.9us
SDA/SCL Rise Timet_r(SDA), t_r(SCL)100020+0.1C_b300ns
SDA/SCL Fall Timet_f(SDA), t_f(SCL)30020+0.1C_b300ns
START Condition Hold Timet_h(ST)40.6us
Repeated START Condition Setup Timet_su(SR)4.70.6us
STOP Condition Setup Timet_su(SP)40.6us
Bus Idle Timet_w(SP:SR)4.71.3us

SPI Serial Peripheral Interface Parameters (V_DD=1.8V, T_A=25degC)

ParameterSymbolTest ConditionsMinTypicalMaxUnit
SPI Clock PeriodT_c(SPC)100ns
SPI Clock FrequencyF_c(SPC)10MHz
CS Setup TimeT_su(CS)5ns
CS Hold TimeT_h(CS)8ns
SDI Input Setup TimeT_su(SI)5ns
SDI Input Hold TimeT_h(SI)15ns
SDO Valid Output TimeT_v(SO)50ns
SDO Output Hold TimeT_h(SO)6ns

Note: 10 MHz clock rate.

SPI Timing Parameters


Functional Description

1. Terminology

1.1 Sensitivity

Accelerometer Sensitivity: The physical quantity describing accelerometer gain, expressed as half the maximum digital output when +/-1G acceleration input is applied. In practice, gravity acceleration is used for measurement. Align the axis under test perpendicular to the ground, record the circuit output value A1, then rotate the axis 180 degrees on any plane, record the output value A2. Compute |A2-A1|, divide by 2, and the result is that axis’s sensitivity. This value varies very little with temperature and time. Another parameter, “sensitivity error,” describes the overall circuit sensitivity range consistency.

Gyroscope Sensitivity: The physical quantity describing gyroscope gain, obtainable by adding a given angular velocity. This sensitivity varies very little with temperature and time. When the sensor rotates counter-clockwise, the axis corresponds to positive digital output.

1.2 Zero Drift

Accelerometer Zero Drift (Zero-g): The deviation between the actual output signal and the ideal output signal when no acceleration is present. On a level surface, the ideal accelerometer output should be 0g for X and Y axes, and 1g for the Z axis. These outputs should be at the center of their respective dynamic ranges; however, in practice there is always deviation — this is the so-called Zero-g offset.

Zero-drift offset is fundamentally a manifestation of MEMS sensors experiencing stress conditions. When a sensor is mounted on a PCB or placed under large-scale mechanical stress, the zero offset will change slightly. Zero offset temperature variation is relatively small. The accelerometer zero-offset tolerance is a batch-level standard deviation of accelerometer sensor zero-offset values.

Gyroscope Zero Drift (Zero-Rate): The deviation of the actual output signal when no angular rate is present. Similarly, this zero offset is a manifestation of MEMS sensors experiencing stress. When mounted on a PCB or placed under mechanical stress, the zero offset will change slightly. Zero offset varies little with temperature and time.

1.3 Self-Test

Accelerometer Self-Test: The self-test function allows testing the mechanical part of the accelerometer without physical motion. The self-test bit is set to “0” to disable self-test. When set to “1,” a driving force is applied to the MEMS mechanical mass, simulating a specific acceleration input. The circuit then outputs external acceleration plus electrostatic drive acceleration data. If the self-test output signal change is within the range specified in this datasheet, the circuit is functioning normally. See register descriptions below for setup details.

Gyroscope Self-Test: The gyroscope self-test function checks the stability of the gyroscope’s drive amplitude, frequency, and drive control loop. It can detect particle contamination, mechanical damage, or stress loss. After initiating gyroscope self-test, the GYR_MEMS_OK result determines whether the gyroscope self-test passed. See register descriptions below for setup details.


2. Operating Mode Description

2.1 Operating Modes

The ICM-42688P has three selectable operating modes:

  1. Accelerometer only active, gyroscope off
  2. Gyroscope only active, accelerometer off
  3. Both gyroscope and accelerometer active simultaneously, with independent ODRs

2.2 Accelerometer Operating Modes

In the ICM-42688P, the accelerometer can be configured into three different operating modes: Off, Low-Power, and High-Performance.

2.3 Gyroscope Operating Modes

In the ICM-42688P, the gyroscope can be configured into four different operating modes: Off, Low-Power, Normal, and High-Performance.

2.4 Operating Mode Settings

ModeSensor TypeACC_ENGYR_ENACC_FILTER_PERFGYR_FILTER_PERFGYR_NOISE_PERF
Standby00XXX
Low-PowerAccelerometer10XXX
Gyroscope01X00
IMU11000
NormalAccelerometer101XX
Gyroscope01X10
IMU11110
High-PerformanceAccelerometer101XX
Gyroscope01X11
IMU11111

3. Digital Interface

The ICM-42688P internal registers can be accessed via I2C and SPI serial interfaces. The SPI interface can be configured as 3-wire or 4-wire mode. When I2C is selected, the CS pin must be tied high (VDD IO).

Pin NamePin Description
CSSPI enable; I2C/SPI mode select (1: I2C mode; 0: SPI enable)
SCL/SPCI2C serial clock (SCL); SPI serial clock (SPC)
SDA/SDI/SDOI2C serial data (SDA); SPI serial data input (SDI); 3-wire SPI serial data output (SDO)
SDO/SA0SPI serial data output SDO; I2C device address LSB SA0

3.1 I2C Serial Interface

The I2C bus interface is a slave device. Data can be written to registers and read from registers via the I2C interface. Related I2C terminology:

TermDescription
TransmitterSends data to the bus
ReceiverReceives data from the bus
MasterInitiates transmission, generates clock signal, terminates transmission
SlaveAddressed by the master for access

The I2C bus uses two signal lines: a serial clock line and a serial data line. The serial data line is bidirectional, allowing the master to send data to the slave and the slave to send data back to the master. Both signal lines are pulled up to VDDIO through pull-up resistors. When the bus is idle, both data lines are high. The I2C interface follows Fast Mode (400 kHz) I2C standard.

3.1.1 I2C Operation

Bus transmission begins with a START signal. The START condition is defined as: while SCL is high, SDA transitions from high to low. The bus is then considered busy. The upper 7 bits of the next byte indicate the master’s target device address; the 8th bit indicates data transfer direction (read/write).

The ICM-42688P slave device address is 0011 00xb (configurable by user). Data transmission requires ACK signal acknowledgment. The transmitter must release the bus on the 9th CLK; the receiver pulls the bus low on the 9th CLK to complete an ACK. The receiver must acknowledge after every byte. The ICM-42688P I2C interface operates as a slave device, following standard I2C protocol (with minor differences). After the START signal, the slave device address is broadcast; when the ACK is received, the sub-register address (lower 7 bits) is sent.

The slave address plus the read/write control bit forms the complete slave device address. If the R/W control bit is “1” (read), the device address and sub-register address are sent. If the R/W control bit is “0” (write), the transfer direction of the next byte remains unchanged.

Master-to-Slave Protocol Sequences

Master writes single byte to slave: Master: ST → SAD+W → – → SUB → – → DATA → – → SP Slave: – → – → SAK → – → SAK → – → SAK → –

Master writes multiple bytes to slave: Master: ST → SAD+W → – → SUB → – → DATA → – → DATA → – → SP Slave: – → – → SAK → – → SAK → – → SAK → – → SAK → –

Master reads single byte from slave: Master: ST → SAD+W → – → SUB → – → SR → SAD+R → – → – → NMAK → SP Slave: – → – → SAK → – → SAK → – → – → SAK → DATA → – → –

Master reads multiple bytes from slave: Master: ST → SAD+W → – → SUB → – → SR → SAD+R → – → – → MAK → – → MAK → – → NMAK → SP Slave: – → – → SAK → – → SAK → – → – → SAK → DATA → – → DATA → – → DATA → – → –

Data is transmitted MSB first on the serial bus, 8 bits per data byte, unlimited number of transmissions. If the receiver is busy processing other tasks and cannot fully receive data, the receiver can pull the SCL line into a wait state, causing the transmitter to wait until the receiver is no longer busy before releasing the SCL bus to continue transmission. If the slave receiver cannot respond to the slave address due to real-time constraints, the SDA line must not be held busy; the master will then terminate the transfer. When SCL is high, a low-to-high transition on SDA constitutes a STOP condition. Each data transmission must end with a STOP condition. For faster data transfer, batch reads or batch writes can be used. The sensor defaults to auto-incrementing the read/write address. For example, after configuration, three-axis accelerometer data can be continuously read (register addresses 0x0C~0x12).

3.1.2 / 3.1.3 I2C Address

The ICM-42688P slave device address is 0011 00xb. The external SDO/SA0 pin can modify the device address LSB. If SDO/SA0 is pulled high, LSB=1 (address = 0011 001b). If SDO/SA0 is tied to ground, LSB=0 (address = 0011 000b). This allows two different inertial sensors on the same I2C bus.

SDO External Connection7-bit I2C Address8-bit I2C AddressNotes
Floating / Logic High0x190x32(W), 0x33(R)No-leakage connection
Logic Low0x180x30(W), 0x31(R)Must disable SDO internal pull-up resistor

3.2 SPI Serial Interface

The SPI bus interface operates as a slave device. Data can be written to registers and read from registers via SPI. The four bus signals are: CSB, SPC, SDI, and SDO.

CSB is the SPI enable signal, controlled by the SPI master — goes low before SPI transfer starts and high after transfer ends. SPC is the SPI serial clock, controlled by the SPI master. SDI and SDO are serial data input and output. Data is clocked on SPC falling edge for input and SPC rising edge for output. Single-byte read/write completes in 16 clock cycles; multi-byte read/write adds 8 clock cycles per additional byte. The first bit (bit0) is sent on the first SPC falling edge after CS goes low.

  • Bit0: R/W bit. 0 = write to circuit, DI(7:0) is data to write; 1 = read from circuit, DO(7:0) is data read out (circuit drives SDO starting at bit8)
  • Bit1-7: Address AD(6:0) is the register address
  • Bit8-15: Data DI(7:0) (write mode), data written to slave device (MSB first); or Data DO(7:0) (read mode), data read from slave device (MSB first)

When Addr_Auto=1, address auto-increments; SDI and SDO functions and behavior remain unchanged.

SPI Timing Parameters (Slave Device)

SymbolParameterMinMaxUnit
tc(SPC)SPI clock cycle100ns
fc(SPC)SPI clock frequency10MHz
tsu(CS)CS setup time6ns
th(CS)CS hold time8ns
tsu(Si)SDI input setup time5ns
th(Si)SDI input hold time15ns
tv(So)SDO valid output time50ns
th(So)SDO output hold time9ns
tdis(So)SDO output disable time50ns

3.2.1 SPI Read

SPI Read Timing

SPI read command completes in 16 clocks. Multi-byte reads add 8 more clock cycles per byte.

SPI Multi-Byte Read

  • Bit0: R/W control bit, set to 1
  • Bit1-7: Address AD(6:0) is the register address
  • Bit8-15: Data DO(7:0) (read mode), data read from slave device (MSB first)
  • Bit16-…: Data DO(…:8) (read mode), additional data (MSB first)

3.2.2 SPI Write

SPI Write Timing

SPI single-byte write command completes in 16 clocks. Multi-byte writes add 8 more clock cycles per byte.

SPI Multi-Byte Write

  • Bit0: R/W control bit, set to 0
  • Bit1-7: Address AD(6:0) is the register address
  • Bit8-15: Data DI(7:0) (write mode), data written to slave device (MSB first)
  • Bit16-…: Data DI(…:8) (write mode), additional data written (MSB first)

3.2.3 SPI 3-Wire Mode Read

SPI 3-Wire Read

3-wire mode is configured by writing 1 to the SIM bit. 4-wire write and 3-wire write use only 3 signal lines with identical logic and timing, so 4-wire write configures the slave device to 3-wire mode first, then 3-wire mode access is used.

SPI read command completes in 16 clocks.

  • Bit0: R/W control bit, set to 1
  • Bit1-7: Address AD(6:0) is the register address
  • Bit8-15: Data DO(7:0) (read mode), data read from slave device (MSB first)

When reading 3-axis FIFO data via SPI, start reading from register 0x0B, continuously read 7 bytes, and use the latter 6 bytes to assemble the 3-axis data. Important: Do not share SPC, MOSI, MISO across multiple SPI devices.

3.3 OIS Interface

The ICM-42688P supports optical image stabilization (OIS) applications via an auxiliary interface. This interface is used to access pre-filtered gyroscope and accelerometer data with minimum latency. Pre-filtered accelerometer data is available when ACC_ODR=1.6kHz; gyroscope data is available when GYR_ODR=6.4kHz. The OIS SPI interface supports 3-wire and 4-wire modes. The OIS SPI interface timing is the same as the main SPI interface.


4. Register Map

4.1 General-Purpose Registers

The following table lists the ICM-42688P general-purpose registers accessible via 8-bit addresses, their addresses, and default values.

NameTypeRegister Address (Hex)Register Address (Binary)DefaultNotes
WHO_AM_Irw010000 00010x6A
Reserved (do not modify)02-03
OIS_CONFrw040000 0100
COM_CFGrw050000 01010x50
INT_CFG1rw060000 0110
INT_CFG2rw070000 0111
HPF&LPF_CFGrw080000 10000x80
DATA_STAT/DATA_STAT_OISr0B0000 1011
ACC_XH/ACC_XH_OISr0C0000 1100output
ACC_XL/ACC_XL_OISr0D0000 1101output
ACC_YH/ACC_YH_OISr0E0000 1110output
ACC_YL/ACC_YL_OISr0F0000 1111output
ACC_ZH/ACC_ZH_OISr100001 0000output
ACC_ZL/ACC_ZL_OISr110001 0001output
GYR_XH/GYR_XH_OISr120001 0010output
GYR_XL/GYR_XL_OISr130001 0011output
GYR_YH/GYR_YH_OISr140001 0100output
GYR_YL/GYR_YL_OISr150001 0101output
GYR_ZH/GYR_ZH_OISr160001 0110output
GYR_ZL/GYR_ZL_OISr170001 0111output
TIME_Hr180001 1000
TIME_Mr190001 1001
TIME_Lr1A0001 1010
FIFO_CFG0rw1C0001 1100
FIFO_CFG1rw1D0001 11010x07
FIFO_CFG2rw1E0001 11100xFF
FIFO_STAT0r1F0001 11110x40
FIFO_STAT1r200010 0000
FIFO_DATAr210010 0001
TEMP_Hr220010 0010
TEMP_Lr230010 0011
AOI1_CFGrw300011 0000
AOI1_STATr310011 0001
AOI1_THSrw320011 0010
AOI1_DURATIONrw330011 0011
AOI2_CFGrw340011 0100
AOI2_STATr350011 0101
AOI2_THSrw360011 0110
AOI2_DURATIONrw370011 0111
CLICK_CRTL_REGrw380011 1000
CLICK_SRCr390011 1001
STEP_CFGrw3A0011 10100x08
STEP_SRCrw3B0011 1011
STEP_COUNTER_Lr3C0011 1100
STEP_COUNTER_Hr3D0011 1101
AOI1&AOI2_CFGrw3F0011 1111
ACC_CONFrw400100 00000xA8
ACC_RANGErw410100 00010x02
GYR_CONFrw420100 00100xA9
GYR_RANGErw430100 0011
FIFO_DOWNSrw450100 01010x88
SOFT_RSTrw4A0100 1010
ACC_SELF_TESTrw6D0110 1101
GRY_SELF_TESTrw6F0110 1111
PWR_CTRLrw7D0111 1101
SEG_SELrw7F0111 1111

Note: Registers marked “Reserved” must not be modified in use — doing so may cause permanent damage. Also, wait 1ms after register configuration before performing register read operations.

4.2 Special Register Bank 1

The following registers require writing 0x83 to register 0x7F (SEG_SEL) before access.

NameTypeHexBinaryDefaultNotes
I2C_UNrw6F0110 1111

Note: After special register configuration, write 0x00 to address 0x7F to return to general-purpose register access. Wait 1ms after configuration before reading registers.

4.3 Special Register Bank 2

The following registers require writing 0x8C to register 0x7F (SEG_SEL) before access.

NameTypeHexBinaryDefaultNotes
DIG_CTRLrw300011 0000

Note: After special register configuration, write 0x00 to address 0x7F to return to general-purpose register access. Wait 1ms after configuration before reading registers.

4.4 Special Register Bank 3

The following registers require writing 0x90 to register 0x7F (SEG_SEL) before access.

NameTypeHexBinaryDefaultNotes
WRIST_SRCrw3E0011 1110
CLICK_COEFF1rw400100 00000x52
CLICK_COEFF2rw410100 00010x9A
CLICK_COEFF3rw420100 00100x04
CLICK_COEFF4rw430100 00110x57
STEP_DELTArw440100 01000x01
STEP_WTMrw450100 01010x01
PEDO_COEFF1rw460100 01100x4F
PEDO_COEFF2rw470100 01110x23
PEDO_COEFF3rw480100 10000xA5
PEDO_COEFF4rw490100 10010x23
PEDO_COEFF5rw4A0100 10100x04
PEDO_COEFF6rw4B0100 10110x8C
WRIST_CTRL1rw510101 00010x30
WRIST_CTRL2rw520101 00100x0F
WRIST_CTRL3rw530101 00110x93

Note: After special register configuration, write 0x00 to address 0x7F to return to general-purpose register access. Wait 1ms after configuration before reading registers.

Do not modify register contents during “boot startup” — these contain factory calibration and compensation data that is power-loss preserved and auto-loaded.


5. Register Descriptions

5.1 WHO_AM_I (01h)

B7B6B5B4B3B2B1B0
01101010

Note: Equivalent to CHIP_ID = 0x6A.

5.2 OIS_CONF (04h)

B7B6B5B4B3B2B1B0
OIS_EN
  • OIS_EN: OIS enable bit. Default: 0 (0: OIS disabled; 1: OIS enabled)

5.3 COM_CFG (05h)

B7B6B5B4B3B2B1B0
BOOTBDUAddr_AutoOSIMSIM
  • BOOT: Reboot trim values. Default: 0 (0: Normal mode; 1: Reboot trim values — auto-resets to “0” after reboot)
  • BDU: Block data update. Default: 0 (0: Continuous update; 1: Output data registers not updated until MSB and LSB are read)
  • Addr_Auto: Communication address auto-increment control. Default: 1 (0: Address does not auto-increment — must be configured for FIFO_DATA continuous reading; 1: Address auto-increments during continuous read/write — suitable for I2C and SPI communication, OIS not applicable)
  • OSIM: OIS SPI communication mode select. Default: 0 (0: OIS 4-wire mode; 1: OIS 3-wire mode)
  • SIM: SPI serial interface mode configuration. Default: 0 (0: 4-wire interface; 1: 3-wire interface)

5.4 INT_CFG1 (06h)

B7B6B5B4B3B2B1B0
INT_PP_ODH_LACTIVEINT1_SEL4INT1_SEL3INT1_SEL2INT1_SEL1INT1_SEL0
  • INT_PP_OD: INT1 and INT2 push-pull or open-drain output select. Default: 0 (0: Push-pull output enable; 1: Open-drain output enable)
  • H_LACTIVE: Interrupt pin default level control. Default: 0 (0: Interrupt triggers output high level — default low; 1: Interrupt triggers output low level — default high)
INT1_SEL[4:0]Description
00001DRDY_ACC interrupt on INT1
00010DRDY_ACC_OIS interrupt on INT1
00011DRDY_GYR interrupt on INT1
00100DRDY_GYR_OIS interrupt on INT1
00101DRDY_TMP interrupt on INT1
00111CLICK interrupt on INT1
01000EMPTY interrupt on INT1
01001WTM interrupt on INT1
01010OVER_FIFO interrupt on INT1
01011AOI1 interrupt on INT1
01100AOI2 interrupt on INT1
01101AOI1|AOI2 interrupt on INT1
01111WTM_STEP interrupt on INT1
10000DELTA_STEP interrupt on INT1
10001OVER_STEP interrupt on INT1
10010WRIST_FLAG interrupt on INT1
10011WRIST_ON_FLAG interrupt on INT1
10100WRIST_DOWN_FLAG interrupt on INT1
10101WRIST_ON_FLAG|WRIST_DOWN_FLAG interrupt on INT1

5.5 INT_CFG2 (07h)

B7B6B5B4B3B2B1B0
INT2_SEL4INT2_SEL3INT2_SEL2INT2_SEL1INT2_SEL0
INT2_SEL[4:0]Description
00001DRDY_ACC interrupt on INT2
00010DRDY_ACC_OIS interrupt on INT2
00011DRDY_GYR interrupt on INT2
00100DRDY_GYR_OIS interrupt on INT2
00101DRDY_TMP interrupt on INT2
00111CLICK interrupt on INT2
01000EMPTY interrupt on INT2
01001WTM interrupt on INT2
01010OVER_FIFO interrupt on INT2
01011AOI1 interrupt on INT2
01100AOI2 interrupt on INT2
01101AOI1|AOI2 interrupt on INT2
01111WTM_STEP interrupt on INT2
10000DELTA_STEP interrupt on INT2
10001OVER_STEP interrupt on INT2
10010WRIST_FLAG interrupt on INT2
10011WRIST_ON_FLAG interrupt on INT2
10100WRIST_DOWN_FLAG interrupt on INT2
10101WRIST_ON_FLAG|WRIST_DOWN_FLAG interrupt on INT2


6D Orientation Detection

6D Orientation Detection

Gyroscope Mounting Orientations

Gyroscope Mounting Orientations


Translated from Chinese datasheet by HuaXuanYang (HXY) Electronics. This is NOT the original InvenSense/TDK ICM-42688-P datasheet — it is a compatible/clone part from HXY with similar register interface. Original document: ICM-42688P-HXY.pdf